In recent years in a secure microcontroller used in an IC card (Integrated Circuit Card) and the like, the operation frequency of the CPU (Central Processing Unit) has been increased, and at the same time, a large capacity nonvolatile memory tends to be mounted. The difference in the operation frequency between the CPU and the large capacity nonvolatile memory becomes significant, and the number of those equipped with a cache memory is increasing to absorb the difference. However, the circuit size and the power consumption are limited to very small values to allow for the use in the IC card and the like.
There have been proposed various types of cache memories. For example, a technique for dividing into instruction cache and data cache, a technique for configuring a cache memory with a plurality of ways, a technique for prefetching of data including an instruction code, and the like. The adoption of these techniques is effective also for the secure microcontroller, but at the same time, it is necessary to meet stringent constraints in terms of circuit size and power consumption.
Techniques for prefetching of data in a cache memory are disclosed in Patent Documents 1 and 2. Patent Document 1 discloses a technique for reading a data block including data to be accessed when a cache miss occurs, and for prefetching a data block in a predetermined adjacent direction. The predetermined adjacent direction is updated following the access history, so that the prefetch direction can be followed to this. Patent Document 2 discloses a technique for preventing actual access from accessing unnecessary ways in a set-associative cache memory with a plurality of ways, by previously reading data which is expected to be read next by predicting which of the ways is the one from which the data will be read.
Patent Document 3 discloses a technique for reading all data for one page at once into a pre-read cache by a row address system selection operation in a nonvolatile memory, and then selecting and reading a part of the data by a column address system operation.